1. Field of the Invention
The present invention relates to a semiconductor device having a circuit constituted of thin film transistors (hereinafter referred to as TFTs) and a method of manufacturing the same. More specifically, the present invention relates to an electro-optical device typified by a liquid crystal display panel and electronic equipment that mounts such an electro-optical device as its component.
It is to be noted that semiconductor devices through this specification refer to devices that can function by utilizing semiconductor characteristics in general, and electro-optical devices, semiconductor circuits, and electronic equipment are all the semiconductor devices.
2. Description of the Related Art
In recent years, development of a semiconductor device having an integrated circuit with large area constituted of thin film transistors (TFTs) formed of a semiconductor thin film (approximately several to several hundred nm in thickness) formed on a substrate having an insulating surface is making progress. An active matrix liquid crystal display device, an EL display device, and a contact type image sensor are known as typical examples of the semiconductor device. In particular, since a TFT in which a crystalline silicon film (typically, a poly-silicon film) is an active layer (hereafter referred to as a poly-silicon TFT) has high field-effect mobility, the TFT can constitute various functional circuits.
For example, in an active matrix liquid crystal display device, a driver circuit for controlling a pixel circuit for displaying images with each functional block and pixel circuits such as a shift register circuit with a CMOS circuit as a base, a level shifter circuit, a buffer circuit, and a sampling circuit is formed on a substrate.
TFTs (pixel TFTs) are arranged in several tens to several million pixels, respectively, in the pixel circuit of the active matrix liquid crystal display device, and the pixel TFTs are provided with pixel electrodes, respectively. An opposing electrode is provided on the side of an opposing substrate sandwiching liquid crystal with the substrate to thereby form a condenser with the liquid crystal as dielectric. The voltage applied to the respective pixels is controlled by a switching function of the TFT to drive the liquid crystal by controlling electric charge to the condenser. Thus, transmission light amount is controlled to display images.
The pixel TFT consists of an n-channel TFT and is driven as a switching element by applying a voltage to the liquid crystal. Since the liquid crystal is driven with an alternating current, a method called frame inversion driving is adopted in many cases. In this method, it is important to sufficiently lower an off current value (a drain current that flows during off operation of a TFT) as a characteristic required to the pixel TFT in order to suppress power consumption.
A lightly doped drain (LDD) structure is known as a TFT structure for reducing an off current value. This structure is such that a region added with an impurity element at low concentration is provided between a channel forming region and a source region or a drain region formed by adding an impurity element at high concentration, and the provided region is called an LDD region. Further, a GOLD (gate-drain overlapped LDD) structure in which an LDD region and a gate electrode are overlapped with each other through a gate insulating film is known as means for preventing deterioration in an on current value due to hot carrier. It is known that such a structure makes a high electric field in the vicinity of a drain to be relaxed to prevent hot carrier injection, and thus, which is effective in preventing deterioration.
Although the GOLD structure is effective in preventing deterioration in an on current value, on the other hand, there has been a problem in that an off current value becomes large in the GOLD structure compared with a general LDD structure. Therefore, the GOLD structure is not preferable for being applied to a pixel TFT. On the contrary, the general LDD structure is effective in suppressing the off current value, but has a little effect in preventing deterioration due to hot carrier injection by relaxing an electric field in the vicinity of a drain. As described above, in a semiconductor device having a plurality of integrated circuits such as an active matrix liquid crystal display device, the above problem clearly exists as, in particular, in a crystalline silicon TFT and is becoming more evident as performance required for the active matrix liquid crystal display device is enhanced.
Conventionally, when the TFT provided with the LDD structure or the TFT provided with the GOLD structure is to be formed, there is a problem in that the manufacturing process becomes complicated and the number of steps increases. It is clear that the increase in the number of steps becomes not only the cause of the increase in manufacturing cost but also the cause of the reduction in manufacturing yield.
The present invention is a technique for solving the above problems, and an object of the present invention is to improve operational characteristics and reliability of a semiconductor device and to realize low power consumption, and also to realize reduction in manufacturing cost and improvement in yield by reducing the number of steps in an electro-optical device and a semiconductor device typified by an active matrix liquid crystal display device manufactured by using TFTs.
Reducing the number of steps may be regarded as a means for realizing the reduction in manufacturing cost and the improvement in yield. Specifically, the number of photo masks required for manufacturing TFTs is reduced. A photo mask is used for forming a resist pattern as a mask on a substrate in an etching step in a photolithography technique. Accordingly, the usage of one photo mask means that a resist peeling step, a washing step, a drying step and the like are added before and after the etching step in addition to a film forming step, the etching step and the like, and that complicated steps such as resist application, pre-baking, exposure, development and post-baking are performed in the photolithography step.
The present invention is characterized in that the number of masks is reduced in comparison with the prior art and a TFT is manufactured by the manufacturing process described below. Note that one example of a manufacturing method of the present invention is shown in FIGS. 1A to 2D.
The structure of the present invention disclosed in this specification is a method of manufacturing a semiconductor device comprising:
a first step of forming a semiconductor layer on an insulating surface;
a second step of forming an insulating film on the semiconductor layer;
a third step of forming a first electrode comprising a lamination of a first conductive layer having a first width (W1) and a second conductive layer on the insulating film;
a fourth step of forming a high concentration impurity region by adding an impurity element to the semiconductor layer using the first electrode as a mask;
a fifth step of forming a second electrode comprising a lamination of the first conductive layer having the first width (W1) and a second conductive layer having a second width (W2) by etching the second conductive layer of the first electrode;
a sixth step of forming a third electrode comprising a lamination of a first conductive layer having a third width (W3) and the second conductive layer having the second width (W2) by etching the first conductive layer of the second electrode: and
a seventh step of forming a low concentration impurity region by adding an impurity element to the semiconductor layer through the first conductive layer or the insulating film using the second conductive layer as a mask.
Further, another example of the manufacturing method of the present invention is shown in FIGS. 3A to 4D. The structure of the present invention is a method of manufacturing a semiconductor device comprising:
a first step of forming a semiconductor layer on an insulating surface;
a second step of forming an insulating film on the semiconductor layer;
a third step of forming a first electrode comprising a lamination of a first conductive layer having a first width (W1) and a second conductive layer on the insulating film;
a fourth step of forming a second electrode comprising a lamination of the first conductive layer having the first width (W1) and a second conductive layer having a second width (W2) by etching the second conductive layer of the first electrode;
a fifth step of forming a high concentration impurity region by adding an impurity element to the semiconductor layer using the second electrode as a mask;
a sixth step of forming a third electrode comprising a lamination of a first conductive layer having a third width (W3) and the second conductive layer having the second width (W2) by etching the first conductive layer of the second electrode; and
a seventh step of forming a low concentration impurity region by adding an impurity element to the semiconductor layer through the first conductive layer or the insulating film using the second conductive layer as a mask.
In the respective manufacturing methods described above, it is characterized in that the second width (W2) is narrower than the first width (W1). Further, in the manufacturing methods, it is characterized in that the third width (W3) is narrower than the first width (W1) and is wider than the second width (W2).
Further, in the respective manufacturing methods, the third step is characterized in that after a first conductive film and a second conductive film are formed in a lamination on the insulating film, the second conductive layer is formed by performing a first etching process with the second conductive film, and the first conductive layer is formed by performing a second etching process with the first conductive film, whereby the first electrode comprising a lamination of the first conductive layer having the first width (W1) and the second conductive layer is formed.
Moreover, still another example of the manufacturing method of the present invention is shown in FIGS. 5A to 6D. The structure of the present invention is a method of manufacturing a semiconductor device comprising:
a first step of forming a semiconductor layer on an insulating surface;
a second step of forming an insulating film on the semiconductor layer;
a third step of forming a first conductive film and a second conductive film in a lamination on the insulating film;
a fourth step of forming a second conductive layer having a first width (X1) by etching the second conductive film;
a fifth step of forming a high concentration impurity region by adding an impurity element to the semiconductor layer through the first conductive film or the insulating film using the second conductive layer having a first width (X1) as a mask;
a sixth step of forming a first electrode comprising a lamination of a first conductive layer having a second width (X2) and a second conductive layer having a third width (X3) by etching the first conductive film;
a seventh step of forming a second electrode comprising a lamination of the first conductive layer having the second width (X2) and a second conductive layer having a fourth width (X4) by etching the second conductive layer of the first electrode;
an eighth step of forming a third electrode comprising a lamination of a first conductive layer having a fifth width (X5) and a second conductive layer having the fourth width (X4) by etching the first conductive layer of the second electrode; and
a ninth step of forming a low concentration impurity region by adding an impurity element to the semiconductor layer through the first conductive layer or the insulating film using the second conductive layer having the fourth width (X4) as a mask.
The above manufacturing method is characterized in that the second width (X2) is narrower than the first width (X1). Further, it is characterized in that the fifth width (X5) is narrower than the second width (X2) and is wider than the fourth width (X4).
Further, still another example of the manufacturing method of the present invention is shown in FIGS. 7A to 8C. The structure of the present invention is a manufacturing method of a semiconductor device comprising:
a first step of forming a semiconductor layer on an insulating surface;
a second step of forming an insulating film on the semiconductor layer;
a third step of forming a first conductive film and a second conductive film in lamination on the insulating film;
a fourth step of forming a second conductive layer having a first width (X1) by etching the second conductive film;
a fifth step of forming a high concentration impurity region by adding an impurity element to the semiconductor layer through the first conductive film or the insulating film using the second conductive layer having the first width (X1) as a mask;
a sixth step of forming a second conductive layer having a second width (Y2) by etching the second conductive layer;
a seventh step of forming an electrode comprising a lamination of a first conductive layer having a third width (Y3) and the second conductive layer having the second width (Y2) by etching the first conductive film; and
an eighth step of forming a low concentration impurity region by adding an impurity element to the semiconductor layer through the first conductive layer or the insulating film using the second conductive layer having the second width (Y2) as a mask.
The above manufacturing method is characterized in that the second width (Y2) is narrower than the first width (X1). Further, it is characterized in that the third width (Y3) is narrower than the first width (X1) and is wider than the second width (Y2).
Furthermore, still another example of the manufacturing method of the present invention is shown in FIGS. 9A to 10B. The structure of the present invention is a method of manufacturing a semiconductor device comprising:
a first step of forming a semiconductor layer on an insulating surface;
a second step of forming an insulating film on the semiconductor layer;
a third step of forming a first conductive film and a second conductive film in lamination on the insulating film;
a fourth step of forming a second conductive layer having a first width (X1) by etching the second conductive film;
a fifth step of forming a high concentration impurity region by adding an impurity element to the semiconductor layer through the first conductive film or the insulating film using the second conductive layer having the first width (X1) as a mask;
a sixth step of forming an electrode comprising a lamination of a first conductive layer having a second width (Z2) and a second conductive layer having a third width (Z3) by etching the first conductive film and the second conductive layer; and
a seventh step of forming a low concentration impurity region by adding an impurity element to the semiconductor layer through the first conductive layer or the insulating film using the second conductive layer having the third width (Z3) as a mask.
The above manufacturing method is characterized in that the third width (Z3) is narrower than the first width (X1). Further, the above manufacturing method is characterized in that the second width (Z2) is narrower than the first width (X1) and is wider than the third width (Z3).
Further, in the respective methods described above, the impurity element is an impurity element that imparts an n-type conductivity or a p-type conductivity to the semiconductor.